An IC is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. IC design layouts typically include circuit modules (e.g., geometric representations of electronic or circuit IC components) with pins, and interconnect lines (e.g., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC. To create the design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts.
A process traditionally performed in the design of the IC is called parasitic extraction. Parasitic extraction is the calculation of parasitic effects (e.g., parasitic capacitances, parasitic resistances and parasitic inductances) in both the designed electronic components and the required wiring interconnects of the IC. The purpose of the parasitic extraction is to create an accurate analog model of the circuit, such that detailed simulations can emulate actual digital and analog circuit responses. Digital circuit responses are often used to populate databases for signal delay and loading calculation such as timing analysis, circuit simulation, and signal integrity analysis. Analog circuits are often run in detailed test benches to indicate if the extracted parasitics may allow the designed IC to function within predetermined specifications.
The manufacturing requirements at advanced process nodes, such as multi-patterning lithography at 0.02 μm, are advancing newer parasitic modeling techniques to achieve signoff accuracy and performance. Multi-patterning lithography is an important technique for ensuring printability of device and interconnect layers in advanced process node manufacturing. However, splitting layers into multiple masks can introduce timing variations because of mask misalignment in the manufacturing process. For example, the misalignment of the layout masks may cause variations in coupling capacitances between the polygons that are on different masks, which in turn affects both the couplings and the total capacitances of the nets.
Errors introduced into the parasitic extraction by multi-patterning depend on mask displacement amount. Impact on coupling capacitance can be large, even while it is smaller on total capacitance, due to the different impact on coupling capacitances at the opposite sides of conductor segments. To enable successful advanced process node manufacturing, a multi-patterning aware modeling solution for parasitic extraction is needed to account for the timing impact and to address the multi-patterning in the physical implementation and signoff design flow.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.